1. Field of the Invention
The present invention relates generally to electronic communication. More specifically, the present invention relates a parallel packetized interconnect with a simplified data link layer.
2. Description of the Related Art
The Peripheral Component Interface (PCI) was a communication standard utilizing parallel busses to connect devices in a computer system topology. While it was extremely popular in its day, it has largely been supplanted by the newer PCI Express (PCIe) standard, which replaces the parallel bus system with a serial, point-to-point scheme.
There are a number of existing devices, however, such as field programmable gate arrays (FPGA) that still utilize parallel interfaces despite the popularity of PCIe. It is therefore desirable to design PCIe switches that are compatible with both PCIe devices and older, parallel interconnect devices.
Traditionally, a parallel packetized interconnect was implemented using a first-in-first-out (FIFO) to FIFO packet based interconnect. One problem is that prior art FIFO-to-FIFO packet based interconnects either don't have error checking mechanisms or, even if they do, there is no ability to backup and replay a portion of the communication once an error, such as a parity error, is detected.
What is needed is a solution that solves these problems.